The OPERATIONAL TRANSCONDUCTANCE AMPLIFIER-CAPACITOR (OTA-C) FILTER is one of the best structures for implementing continuous-time FILTERs. It is particularly important to design a universal OTA-C FILTER capable of generating the desired FILTER response via a single structure, thus reducing the FILTER circuit power consumption as well as noise and the occupied space on the electronic chip. In this study, an inverter-based universal OTA-C FILTER with very low power consumption and acceptable noise was designed with applications in bioelectric and biomedical equipment for recording biomedical signals. The very low power consumption of the proposed FILTER was achieved through introducing bias in subthreshold MOSFET transistors. The proposed FILTER is also capable of simultaneously receiving favorable low-, band-, and high-pass FILTER responses. The performance of the proposed FILTER was simulated and analyzed via HSPICE software (level 49) and 180 nm complementary metal-oxide-semiconductor technology. The rate of power consumption and noise obtained from simulations are 7.1 nW and 10.18 nA, respectively, so this FILTER has reduced noise as well as power consumption. The proposed universal OTA-C FILTER was designed based on the minimum number of TRANSCONDUCTANCE blocks and an inverter circuit by three TRANSCONDUCTANCE blocks (OTA).

The study of low power wireless radio systems is an area in modern defense that especially deals with higher performance FILTERs. In recent years, Gm-C FILTERs have drawn attention due to their high frequency performance and integrability. In this paper, a fourth-order low-pass Gm-C FILTER with on-chip automatic tuning circuit is presented. The core of this FILTER is a low-voltage high-frequency CMOS inverter-based OPERATIONAL TRANSCONDUCTANCE amplifier (OTA). To improve the linearity of the OTA, a new common-mode feedback (CMFB) circuit is presented that is combined with a common-mode feedforward (CMFF) circuit. Moreover, a new automatic tuning circuit is presented. By tuning the bulk voltage of transistors, this circuit compensates the effects of mismatches and temperature changes on the OTA, and therefore, on the FILTER cutoff frequency. Furthermore, this circuit consumes small portion of the power consumed by the FILTER. The circuits are designed and simulated in Cadence using TSMC 90nm CMOS technology and a 1 V power supply. The post-layout simulation results show that the DC differential gain, common-mode gain,-3 dB cutoff frequency and unity-gain frequency of the OTA are 34. 7 dB,-26 dB, 255 MHz and 13. 8 GHz, respectively. The cutoff frequency of the FILTER is 1 GHz, and by applying 0. 2 Vp-p input voltages, the third-order intermodulation (IM3) of the FILTER at the cutoff frequency is-38 dB. The power consumption and the area of the FILTER are 4. 8 mW and 0. 043 × 0. 038 mm2, respectively. Moreover, Monte Carlo simulations show the good robustness of proposed FILTER against the process errors.

The electrocardiogram is affected by various noises and one of the most important of which is 50 Hz power-line noise. On the other hand, it is necessary to use a battery in the portable device and so it requires the use of low power consumption circuits. Therefore, one of the challenges ahead when designing this type of device is the use of energy-saving FILTERs with the ability to integrate devices and attenuate unwanted signals properly. This paper presents a low-power tunable sixth-order band-stop FILTER that does not need the off-chip capacitors. The FILTER structure is based on OPERATIONAL TRANSCONDUCTANCE amplifiers (OTA) and integrated capacitors. Also, it is possible to change the central attenuation frequency of the proposed FILTER using bias voltage of the TRANSCONDUCTANCE amplifiers. The proposed band-stop FILTER is designed and simulated in 180 nm CMOS technology at the transistor level. The simulation results show that the proposed FILTER can attenuate unwanted signals at 50 Hz by 102 dB while the maximum capacitance used in the FILTER is 54 pF. The power consumption of the proposed band-stop FILTER is 13.1 nW at a supply voltage of 1.8 V.

High dynamic range and adjustability of gain are the main requirements in low-voltage audio-frequency transconductors. There are several methods for designing a low voltage transconductor however, most of them have a fixed TRANSCONDUCTANCE over their input range. In this paper a low distortion ohmic transconductor with adjustable gain has been designed. The circuit can operate from 3 V single power supply and has a very low distortion by choosing normal dimension for W/L of feedback transistors. To consider stray capacitances of the circuit we also perform L-Edit extraction. Then the final circuit has been carried out with 0.8.um CMOS Technology. Simulation has resulted a very low distortion as small as 0.2% for a 1.8Vpp sinusoidal input.

A novel low-voltage two-stage OPERATIONAL amplifier employing resistive biasing is presented. This amplifier implements neutralization and correction common mode stability in second stage while employs capacitive dc level shifter and coupling between two stages. The structure reduces the power consumption and increases output voltage swing. The compensation is performed by simple miller method. For each stage an independent commonmode feedback circuits has been used. Simulation results show that power consumption is 2.1 mW at 1 V supply. The dc gain of the amplifier is about 70 dB while its output swing is as high as around 1.2 V.

With advancement of integrated circuit technology and aggressive scaling into nanometer regime, statistical variability in device electrical characteristics caused by discreteness of charge and fabrication process variations has significantly increased. These variations in turn result in fluctuations in output characteristics of important analog building blocks and in particular, amplifiers. In this paper, with the aid of Monte-Carlo simulations for a TRANSCONDUCTANCE amplifier and using 1000 different compact models of MOSFET transistors in 35nm technology node, statistical variations of important circuit parameters are investigated and analyzed based on their statistical distributions. Moreover, statistical correlations between circuit parameters are extracted. Analysis of statistical variations for circuit parameters and their correlations has a direct impact on reduction of cost and time of a design and thus, is of great amount of significance.

A novel gain boosted folded cascode Op-Amp using simple single stage auxiliary amplifiers is presented. The proposed auxiliary amplifiers are designed in a way that have proper input and output DC common mode voltage without using common mode feedback network. The inputs of the auxiliary amplifiers are insulated by the coupling capacitors and floating-gate MOS transistors. Thus, the DC input voltage level limit has been removed. Diode connected transistors are also used in the output of the auxiliary amplifiers, which keep the output voltage level at the desired. A simple single stage auxiliary amplifier imposes fewer poles and zeroes on the main amplifier compared to more complicated amplifiers where consumes also less power consumption. Simulation results in a 0.18μm CMOS technology show a DC gain enhancement of about 20dB while output swing, slew rate, settling time, phase margin and gain-bandwidth retain almost as the same as previous folded cascode design.

Probabilistic data structures are so popular in membership queries, network applications, and databases and so on. Bloom FILTER and Cuckoo FILTER are two popular space efficient models that incorporate in set membership checking part of many important protocols. They are compact representations of data that use hash functions to randomize a set of items. Being able to store more elements while keeping a reasonable false positive probability is a key factor of design. A new algorithm is proposed to improve some of the performance properties of Cuckoo FILTER such as false positive rate and insertion performance and solve some drawbacks of the Cuckoo algorithm such as endless loop. Main characteristic of the Bloom FILTER is used to improve Cuckoo FILTER, so we have a smart Cuckoo FILTER which is modified by Bloom FILTER so called as SCFMBF. SCFMBF uses the same table of buckets as Cuckoo FILTER but instead of storing constant Fingerprints, it stores Bloom FILTERs. Bloom FILTERs can be accumulated in the table’ s buckets which leads to higher insertion feasibility. We also address the endless loop problem of Cuckoo FILTER that means an inserted item is stuck in an iterative process of finding an empty bucket, so a smart algorithm is designed which not only solves endless loop problems but also prevents insertion failure. Hence our smart algorithm prevents double checking of a bucket and avoids making loops. Consequently, the capacity of SCFMBF is improved significantly. Results of comparison with Cuckoo FILTER shows that false positive probability of SCFMBF method is enhanced compared to Cuckoo FILTER.

This paper is based on analysis of a common source-common gate low noise TRANSCONDUCTANCE amplifier (CS-CG LNTA). Conventional noise analyses equations are modified by considering to the low output impedance of the sub-micron transistors and also, parasitic gate-source capacitance. The calculated equations are more accurate than calculated equations in other works. Also, analyses show that the noise of the tail transistor, which is utilized to bias the common gate transistor, will limit noise canceling advantages. So, the common gate transistor is biased by a resistor. That leads to a significant improvement in noise figure. By utilizing a Taylor series expression, a closed-form equation is obtained to calculate IIA3 for the first time. Finally, based on the calculated equation a design procedure is proposed.